#define     CKMUX_TOKEN                 0x5A3C              //X1_APB SLAVE1

#define     SCU_BASE                    0x4201A000

#define     CMU_BASE                    SCU_BASE+0x0
#define     RMU_BASE                    SCU_BASE+0x00000100
#define     ACR_BASE                    SCU_BASE+0x00000200
//CMU
#define     CMU_CKMUX_SEL               CMU_BASE+0x00
#define     CMU_SDMMC0_DIV              CMU_BASE+0x04
#define     CMU_SDMMC1_DIV              CMU_BASE+0x08
#define     CMU_OSPI0_DIV               CMU_BASE+0x0C
#define     CMU_OSPI1_DIV               CMU_BASE+0x10
#define     CMU_GMAC125M_DIV            CMU_BASE+0x14
#define     CMU_LSP_DIV                 CMU_BASE+0x18
#define     CMU_HSP_DIV                 CMU_BASE+0x1C
#define     CMU_AXI_DIV                 CMU_BASE+0x20
#define     CMU_AHB_DIV                 CMU_BASE+0x24
#define     CMU_CKEN_SW                 CMU_BASE+0x28

//CMU
#define     RMU_SW_RST                  RMU_BASE+0x40
#define     RMU_SW_RST1                 RMU_BASE+0x44
#define     RMU_RST_FLAG                RMU_BASE+0x48

//ACR (Analog_Control_Reg)
#define     PLL0_CFG0                   ACR_BASE+0x00
            //b31    , PLL0_PD
            //b30    , PLL0_DACPD        
            //b29    , PLL0_DSMPD        
            //b28    , PLL0_FOUT4PHASEPD 
            //b27    , PLL0_FOUTPOSTDIVPD
            //b26    , PLL0_FOUTVCOPD    
            //b25    , PLL0_BYPASS       
            //b24    , RO,LOCKED
            //b21:b16, PLL0_REFDIV,1~63
            //b11:b0 , PLL0_FBDIV,Integer:16~3800, Frac:20~380
#define     PLL0_CFG1                   ACR_BASE+0x04
            //b30:b28, PLL0_POSTDIV2
            //b26:b24, PLL0_POSTDIV1
            //b23:b0 , PLL0_FRAC
#define     PLL1_CFG0                   ACR_BASE+0x08
#define     PLL1_CFG1                   ACR_BASE+0x0C

#define     GLB_REG0                    ACR_BASE+0x10
